A 10-bit 100-kS/s Successive Approximation Register ADC with improved Split Capacitor-based DAC
نویسندگان
چکیده
A 10-bit 100-kS/s successive approximation register (SAR) analogto-digital converter (ADC) with rail-to-rail input range is proposed for a low power sensor interface. It consists of a time-domain comparator, a split capacitor-based digital-to-analog converter (SC-DAC) and a SAR logic. The time-domain comparator with an offset calibration technique is used to achieve a resolution of 10-bit. To reduce process variation, the value of a split capacitor in the SC-DAC is adjusted to enhance the linearity of the SC-DAC. The proposed 10-bit 100-kS/s SAR ADC is designed using a 0.11-μm CMOS process with a 1 V supply. The power consumption and active area of SAR ADC are 7.49 μW and 0.1056 mm. The maximum SNDR is 60 dB for the analog input frequency of 1.023 kHz when the value of a split capacitor in the SC-DAC is optimized.
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